1. Field of the Invention
The present invention generally relates to digital voltage level shifter circuits and more specifically to a level shifter circuit to shift a signal from a low voltage domain to a high voltage domain without a direct current leakage path.
2. Description of the Related Art
Conventional integrated circuit devices use different voltage levels for different logic blocks within a single integrated circuit device. Logic blocks that have critical timing typically operate using a higher power supply compared with logic blocks that do not have critical timing. While it is desirable to use a lower power supply in order to reduce power, some logic blocks require a higher power supply to meet performance requirements. A voltage level shifter circuit is used to convert the voltage level of signals to transmit those signals between logic blocks that operate using different supply voltages.
FIG. 1 illustrates a level shifter circuit 100 configured to shift signals from a low voltage domain that uses a VDDL voltage supply to a high voltage domain that uses a VDDH voltage supply, according to the prior art. Circuit 100 includes two PMOS transistors, 115 and 135 and two NMOS transistors, 110 and 130. VDD 125 is set to VDDH and ground 220 is set to the ground voltage of 0 volts. The input 105 ranges between ground and VDDL and the output 150 should range between ground and VDDH. When input 105 is a logical false (ground voltage), transistors 110 and 135 are off and transistors 115 and 130 are activated, and output 150 is discharged to the ground voltage.
When input 105 is a logical true (VHHL), transistor 130 is off, transistors 110 and 135 are activated. Transistor 115 is partially or fully activated depending on the value of VDDH, VDDL, and the device threshold voltage (Vth). Assuming a VDDL of 0.8V+/−10%, VDDH of 1.0V+/−10%, and Vth=100 mV (fast-fast process corner) and ˜350 mV (slow-slow process corner), the worst case conditions are VDDL=0.72V, VDDH=1.1V, and Vth=200 mV. The voltage at the source of transistor 115 is 1.1V and the voltage at the gate of transistor is 0.72V, producing a gate-to-source voltage (Vgs) of 380 mV which is larger than the threshold voltage of 200 mV, so transistor 115 is activated. When transistors 115 and 110 are both fully activated there is a direct current path between VDD 125 and ground 120, which consumes a lot of power. In order to reduce the power consumed to shift the voltage levels of signals between different power domains, a dual rail input level shifter circuit may be used.
FIG. 2 illustrates a level shifter circuit 200, configured to shift signals from a low voltage domain to a high voltage domain using dual rail inputs, according to the prior art. Input_b 205 and input 245 are complimentary signals. Circuit 200 includes two PMOS transistors, 215 and 235 and two NMOS transistors, 210 and 230. VDD 225 is set to VDDH and ground 220 is set to the ground voltage of 0 volts. Input_b 205 and input 245 each ranges between ground and VDDL and output 250 should range between ground and VDDH. When VDDL is applied to input 245 and a logical zero (ground voltage) is applied to input_b 205, transistors 215 and 230 are activated. Node 212 is charged to VDDH and node 232 is discharged to the ground voltage. The inverter 240 charges output 250 to VDDH and there is no direct current flowing between VDD 225 and ground 220. However, circuit 200 requires two inputs instead of a single input to level shift each signal from the low voltage domain to the high voltage domain, doubling the number of wires that are routed to each voltage level shifter circuit 200. In circuit designs that are routing limited, it is desirable to use a single rail input instead of a double rail input circuit.
Accordingly, what is needed in the art is a system and method for shifting the voltage level of signals from a low voltage domain to a high voltage domain using a single input without producing a direct current leakage path.